1. Field of the Invention
The present invention relates generally to a method and apparatus for setting write latency in a memory system. More particularly, the present invention relates to a write latency procedure and apparatus which reduce the risk of data stored in memory being defective due to the memory improperly receiving a write enable (RxEn) signal too early or too late in relation to the data and the preamble of the data clock to compensate for timing variations occurring after initialization.
2. State of the Art
Many integrated circuits and electronic devices use memory systems for storing data. Over time, the need for smaller and faster circuits and devices has reduced the tolerance for error, particularly in data transfer systems. Errors in a data storage system slow the system by requiring additional data transfer or causing the system to use unreliable or incorrect data.
The data transmission rate of modem integrated circuits is primarily limited by internal circuitry operating speeds. That is, communication networks have been developed which can transmit signals between circuitry at a rate that is faster than the capacity of many integrated circuits. To address the need for faster circuits, a group of integrated circuits can be on a common bus. In this configuration, each integrated circuit operates in a coordinated manner with the other integrated circuits to share data which is transmitted at a high speed. An example of such a high-speed data system is described in U.S. Pat. No. 5,917,760 to Millar (Jun. 29, 1999), incorporated herein by reference. Millar describes a high-speed data system using a common bus and a memory subsystem commonly known as SyncLink dynamic random access memory (xe2x80x9cSLDRAMxe2x80x9d). By providing an appropriate number of memory devices and an efficient control system as used in SLDRAM, very high-speed data transmission can be achieved.
In computer memory systems, particularly in what is often termed the main memory, information is typically stored in dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) integrated circuits. A memory controller manages the operations of the DRAMs. Some of the operations which are managed by the memory controller for DRAMs are read and write operations. A read operation of a memory controller typically includes the following steps: 1) initiating, via the memory controller, the read operation; 2) generating the row address strobe/column address strobe (RAS/CAS) memory timing signals and applying them, to the memory bank targeted by the read operation; 3) once the read data is available on the bank""s memory data bus, buffering the read data into a buffer coupled to the memory bank; and 4) transferring the data from the memory buffer into a data path buffer for storage until the data is placed onto the processor bus for transmission to the processor or device requesting the data. In synchronous read operations such as those performed in SLDRAM, an output of data on the data bus results from a read command and an address received at a preceding leading edge of the clock. The delay in the number of clock cycles between the arrival of the read command at the input to the control logic and the availability of data at the data bus is the xe2x80x9clatencyxe2x80x9d of the DRAM. In other words, the memory controller sends a read command to the DRAM based upon the latency setting which is programmed into the DRAM as part of an initialization process. The DRAM accesses its own stored data and returns the requested data at the appropriate time.
Distinct from a read operation, in a write operation the data is not yet stored in the DRAM. Therefore, upon receiving a write command, the DRAM must know ahead of time when the data will arrive in relation to the write command so that it can begin write operations at the correct time. The delay in clock cycles from the arrival of the write command to the beginning of the data is the write latency. A clock xe2x80x9ctickxe2x80x9d is one-half of a clock cycle, meaning that a clock cycle is the duration between the beginning of a clock cycle to the beginning of the next full clock cycle and a clock tick is only the duration between a falling and a rising (or a rising and a falling) edge of the clock signal. Because the DRAM is dependent upon surrounding systems for supplying both the write command and the data to be written, the latency setting is crucial to obtaining accurate data storage. In response to the write command, the DRAM generates a write enable (RxEn) signal based upon the latency setting. If the internally generated write enable (RxEn) signal fires too far ahead of the data to be written or too close to the data, data may be missed, or incorrect data may be stored. In either case, poor latency settings create reliability and efficiency problems. A write operation typically includes the following steps: 1) transferring the write data from the data path in the memory subsystem to a specified memory device; 2) initiating, via the memory controller, the write operation; and 3) internally generating the necessary memory timing signals and applying them to complete the write operation.
Latency settings in a memory system are established during initialization wherein the data transfer and data receive rates and timing are evaluated so that the subsystems can interfunction with other subsystems by reference to a common clock rate. The latency settings remain unchanged by the system until another initialization process is performed. During initialization of a memory system, the latency for DRAM is set to optimize system performance and to match up the DRAM latency to that expected by the memory controller. After latency settings are chosen during initialization of a system, the system typically changes to a normal operating mode wherein the read and write functions of the memory can be carried out.
In SLDRAM memory systems, there are primarily two methods used for establishing write latency. The first method involves performing a series of sequential writes to and reads from memory address locations while varying the write latency in the SLDRAM or the memory controller for each sequential write. The read and write data are then compared to determine which write latency settings for the SLDRAM match a write latency setting for the memory controller, resulting in valid data. When all of the address locations are read back, good data indicates a match between the DRAM write latency and that of the memory controller. The second method involves a long succession of back-to-back writes to varied address locations performed in a walking pattern. For each new write, the memory controller presents the data and data clock signal (xe2x80x9cDCLKxe2x80x9d) to the data bus one tick later than the previous write. This allows the write data to xe2x80x9cwalkxe2x80x9d through the point at which the DRAM enables its input buffers. Whenever the data and DCLK signals correctly align with the receiver enable signal, the write operation will capture and store the data correctly. The data at each memory address is then read back starting at the first write address. By analyzing the data pattern at each memory address, the amount of offset between the SLDRAM""s and the memory controller""s write latencies can be determined and set appropriately.
With reference to FIG. 1, in either of the above two methods, a valid write latency setting is indicated when the write enable (RxEn) signal 2, also called the receiver enable signal, transitions at the SLDRAM receiver 4, shown in FIG. 2, during the low preamble 6 of the DCLK signal 8. The preamble period is typically either two or three ticks in duration. FIG. 1 shows a three-tick preamble 6, meaning the DCLK signal 8 is low for a duration of three clock ticks. Two-tick preambles are also common. If the RxEn signal 2 transitions within the preamble 6, the SLDRAM will be able to accurately receive and store the data within the oscillation portion 10 of the DCLK signal 8. However, if the RxEn signal 2 transitions before or after the preamble period, the DRAM will capture data incorrectly and store defective information. So long as the RxEn signal 2 transitions within the preamble 6 of the DCLK signal 8, the latency is considered acceptable. Thus, there are often several latency settings which meet this criteria and are acceptable.
One problem that occurs using write latency settings established in this way is that as the system warms up, its characteristics change, including the speeds at which it transfers data between points. This often results in latency settings set at initialization which become insufficient because the write enable (RxEn) signal no longer fires within the preamble. This results in slower memory performance and more frequent data errors. Furthermore, in using latency settings established as described above, without specifically checking whether the stored data is correct by comparing it with the sent data, a system cannot know whether the data upon which it is relying from the memory subsystem is accurate. However, running frequent initialization processes to reset latency, or checking the accuracy of every data signal, would eliminate the benefits of high-speed data transfer and temporary data storage systems. It is, therefore, desirable in the art to have a system which can more reliably store data in a way which is unaffected by system and environmental variations after initialization and latency setting.
The present invention addresses the problem of latency settings made during initialization which subsequently become unreliable due to system timing changes as the circuitry warms up. Most generally, the method of setting write latency comprises establishing an acceptable region within the preamble of a clock signal (DCLK) wherein the edges of the acceptable region are distinct from the edges of the preamble, and determining whether a write enable (RxEn) signal transitions within the acceptable region. Most preferably, the edges of the acceptable region are sufficiently spaced from the edges of the preamble so that any latency setting which causes the write enable (RxEn) signal to transition within the acceptable region during initialization will still cause the write enable (RxEn) signal to transition within the preamble after the system has reached its most extreme timing variations.
In one embodiment of the present invention, the acceptable region within the preamble is established by creating unacceptable regions within the preamble near each of the edges of the preamble. A first unacceptable or margin region established near the first edge of the preamble is established by delaying the clock signal (DCLK). In this way, the timing difference between the undelayed clock signal and the delayed clock signal becomes a first unacceptable region. A second unacceptable or margin region established near the second edge of the preamble is established by delaying the write enable (RxEn) signal. In this way, the timing difference between the undelayed write enable (RxEn) signal and the delayed write enable (RxEn) signal becomes a second unacceptable region. Most preferably the signal delays are accomplished using variable delay elements.
In another embodiment of the present invention, a reset signal is used to reset the system prior to the preamble of the clock signal (DCLK). In a specific embodiment, the reset signal is a write command signal which pulses low.
In yet another embodiment of the present invention, in addition to setting the acceptable region within the preamble of the clock signal, the present invention includes determining or indicating whether the write enable (RxEn) signal transitions within the acceptable region of the preamble for the present latency setting. In one embodiment, a detector enables associated comparators upon locating a leading edge of the preamble by identifying the first high to low transition of the clock signal (DCLK) following a circuit reset signal. A first, enabled comparator determines whether a transition from the first or leading edge of a delayed clock signal (DCLK) occurs prior to a transition in a write enable (RxEn) signal. A second, enabled comparator determines whether a transition from a delayed write enable (RxEn) signal occurs prior to a transition from the second or following edge of an undelayed clock signal (DCLK). An evaluator then evaluates the output from each comparator to determine if the latency setting being tested acceptably causes the write enable (RxEn) signal to transition within the preamble of the clock signal (DCLK). The evaluator then indicates if the latency setting is acceptable or unacceptable.
In a further embodiment, in addition to setting the acceptable region within the preamble of the clock signal, a first arbiter determines whether a delayed clock signal (DCLK) transitions prior to the write enable (RxEn) signal transition, in which case the write enable (RxEn) signal transition was not prior to or within the margin region nearest the first or leading edge of the preamble. A second arbiter then determines whether a delayed write enable (RxEn) signal transitioned prior to the second or following edge of the preamble, in which case the write enable (RxEn) signal transition was not after or within the margin region nearest the second edge of the preamble. If the write enable (RxEn) signal is prior to or within the margin region nearest the first edge of the preamble, or after or within the margin region nearest the second edge of the preamble, the latency setting being tested is unacceptable. In such an instance, the latency setting is changed and the process begins again to test the new latency setting. Contrarily, if the write enable (RxEn) signal transitions between the margin regions, the latency setting being tested is acceptable and a signal indicating the acceptability is produced. Optionally, the indication of acceptability may be stored in a memory register for reading by the memory controller.
The present invention also includes a circuit for use with the method described herein. The circuit comprises delay circuits to delay the necessary signals, and arbiters, or temporal comparators to determine the priority and timing of signals to indicate whether the latency settings used acceptably allowed the write enable (RxEn) signal to transition within the preamble, yet sufficiently separated from the edges of the preamble to avoid shifting outside the preamble after initialization.